(a) Field of the Invention
The present invention relates to a method of forming a dual damascene pattern in a fabrication process of a semiconductor device, and more particularly to a method of forming a dual damascene pattern of a semiconductor device, which is capable of simplifying a fabrication process of a semiconductor device by filling a via hole with a photoresist, using a reflow phenomenon of the photoresist, in an ashing process after the via hole is formed.
(b) Description of the Related Art
Conventional methods of forming a dual damascene pattern in a fabrication process of a semiconductor device include a step of applying a first photoresist having a window of a prescribed size to function as a mask on a top surface of the semiconductor substrate on which a copper wire, a first nitride film, a first interlayer dielectric, a second nitride film, and a second interlayer dielectric are formed in order, a step of forming via holes by etching a region of the semiconductor substrate corresponding to the window of the first photoresist up to a nitride film using a dry or wet etching process, a step of removing a photoresist by ashing the photoresist at a high temperature in an ashing equipment, a step of filling the via holes with the second photoresist or an organic ARC (anti-reflection coating) in a photo track equipment, a step of applying a third photoresist functioning as a mask and having a window larger than the via holes on an interlayer dielectric, a step of forming metal line hollows by etching a region of the semiconductor substrate corresponding to the window of the third photoresist up to a nitride film using a dry or wet etching process, and a step of removing the third photoresist by ashing the third photoresist at a high temperature.
Here, the reason for filling the via holes with the second photoresist or the organic ARC in the photo track equipment is that contamination of a lower copper wire layer is prevented and a metal line hollow profile makes good.
However, in the conventional dual damascene pattern formation methods, since the via holes are formed, the first photoresist as the mask of the via holes is completely removed in the ashing equipment, and then the via holes are filled with the second photoresist or the organic ARC in the photo track equipment, the number of fabrication processes unnecessarily are increased, which results in increase of probability of contamination of the semiconductor device.
In addition, a problem arises in that voids frequently occur as the via holes are not completely filled with a photoresist in the photo track equipment.
Conventional techniques related to the dual damascene process as described above are disclosed in U.S. Pat. Nos. 6,589,881, 6,458,689, and 5,935,762.
In considerations of the above problems, it is an object of the present invention to simplify a fabrication process of a semiconductor device.
Another object of the present invention is to prevent occurrence of voids when via holes are filled with a photoresist.
Still another object of the present invention is to fill via holes with a photoresist using a reflow phenomenon of the photoresist.
To achieve the objects, according to an aspect of the present invention, a method of forming an interlayer dielectric on a structure of a semiconductor substrate; forming a first photoresist having a first window of a predetermined width on the interlayer dielectric; forming via holes by etching the interlayer dielectric exposed through the first window using the first photoresist as a mask; filling the via holes with the first photoresist by reflowing the first photoresist and removing the first photoresist on the interlayer dielectric, in an ashing process to raise an atmosphere temperature; forming a second photoresist having a second window of a width larger than that of the first window and exposing the first photresist and a portion of the interlayer dielectric through the second window on the interlayer dielectric; forming metal line hollows by etching the interlayer dielectric and the first photoresist exposed through the second window up to a depth shallower than that of the via holes using the second photoresis as a mask; and removing residual first and second photoresists.
Preferably, in the ashing process, a step of filling the via holes with the first photoresist by reflowing the first photoresist and a step of removing the first photoresist on the interlayer dielectric is performed sequentially or simultaneously.
Preferably, when a step of filling the via holes with the first photoresist by reflowing the first photoresist and a step of removing the first photoresist on the interlayer dielectric is performed simultaneously, the ashing process is performed under the conditions where a duration is 10 to 40 seconds, a temperature is 150 to 300xc2x0 C., a pressure is 0.5 to 5 Torr, a injection of O2 is 500 to 10000 ions/cm2, a injection of N2 is less than 1000 ions/cm2, and a power is 200 to 2000 W.
Preferably, in the ashing process, a first step of removing a polymer generated in the step of forming the via holes, a second step of filling the via holes with the first photoresist by reflowing the first photoresist, a third step of removing the first potoresist on remaining interlayer dielectric except the filling first photoresist are performed sequentially.
Preferably, the first step of removing the polymer generated in the step of forming the via holes is performed under the conditions where a duration is 3 to 20 seconds, a temperature is 150 to 300xc2x0 C., a pressure is 0.5 to 5 Torr, a injection of O2 is 500 to 10000 ions/cm2, a injection of N2 is less than 1000 ions/cm2, and a power is 200 to 2000W.
Preferably, the second step of filling the via holes with the first photoresist by reflowing the first photoresist is performed under the conditions where a duration is 10 to 200 seconds, a temperature is 150 to 300xc2x0 C., a pressure is 0.5 to 5 Torr, a injection of O2 is 500 to 10000 ions/cm2, a injection of N2 is less than 1000 ions/cm2, and a power is 0W.
Preferably, the third step of removing the first photoresist on remaining interlayer dielectric except the filling first photoresist is performed under the conditions where a duration is 5 to 20 seconds, a temperature is 150 to 300xc2x0 C., a pressure is 0.5 to 5 Torr, a injection of O2 is 500 to 10000 ions/cm2, a injection of N2 is less than 1000 ions/cm2, and a power is 200 to 2000W.
Preferably, the interlayer dielectric includes a first etch stop layer, a first dielectric, a second etch stop layer and a second dielectric, wherein, in the step of forming the via holes, the first etch stop layer is exposed by etching the second dielectric, the second etch stop layer and the first dielectric, and wherein, in the step of forming the metal line hollows, the second etch stop layer is exposed by etching the second dielectric.
Preferably, the first etch stop layer and the second etch stop layer are a nitride layer.
Preferably, the uppermost layer of the structure of the semiconductor substrate is a copper wire layer.
Preferably, in the step of removing the residual first and second photoresists, the residual first and second photoresists are removed by combustion.
Preferably, in the step of forming the via holes and the step of forming the metal line hollows, the interlayer dielectric and the first photoresist are dry or wet etched.